Semiconductor memory device with fast successive read operation
US5748561A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Nov 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device of the invention includes a memory cell array having a plurality of memory cells, row selector for selecting a row of the memory cell array corresponding to a row address of an input address, and column selector for selecting a plurality of columns of a memory cell array corresponding to a column address of an input address, and also selecting a plurality of columns of a memory cell array corresponding to at least one column address other than a column address of an input address. The device also includes a sense amplifier for sensing data stored in memory cells. The sense amplifier has at least two sense amplifier groups, the sense amplifier groups sensing data read from a plurality of memory cells corresponding to an input address, and data read from a plurality of memory cells corresponding to the row address of an input address and at least one other column address. The device has a page mode for rapidly switching and outputting data from a plurality of memory cells which have been read in parallel to sense amplifier in accordance with an input address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.