Integrated network switch with flexible serial data packet transfer system
US5748627A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 1994 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Jun 10, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/0407
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an elastic linear buffer. The buffer is arranged in a closed loop, so that upon reaching the last address, the message is wrapped around and writing continues from the first address. Three markers are provided: a write pointer, which indicates the address of the data currently being stored; a head pointer, which indicates the last address of a previously recorded message; and a tail pointer, indicating the address of the data last read from the buffer. When the last bit of a presently received message is recorded, the head pointer is updated to indicate the address of that bit. Thereafter, a message is sent to the CPU which may commence reading of the message just received. Concurrently, a newly received message can be recorded at the addresses following the address of the head pointer up to the address of the tail pointer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.