Clock scan design from sizzle global clock and method therefor
US5748645A · kind A · utility
22Cited by
8References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | May 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan based test methodology generates conventional functional clocks (CLK1 and CLK2) and test clocks (CLKA and CLKB) from a single input clock (GCLK). The methodology allows an integrated circuit (10) designed according to it to be tested at the part's operating frequency. Also, the test methodology is compatible with known test methodologies such as level sensitive scan design ("LSSD"). The pre-existing body of test programs and equipment can be used with a circuit incorporating the invention. The single clock requirement also simplifies design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.