Dual bus architecture for a storage device
US5748871A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1995 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Aug 11, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1014
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first bus, a second bus, and a storage module having a first and second output with the first output being connected to the first bus and a second output being connected to the second bus. A first buffer storage and a second buffer storage in which the first buffer storage is connected to the first bus and the second buffer storage is connected to the second bus. The second buffer storage includes an error correction module. First and second network adapters are connected to the first and second buses respectively. The first network adapter also includes a connection to the first buffer. A processor in the apparatus includes a first processor circuitry for transferring the data using a first path through the first output in the storage module to the first buffer storage and from the first buffer storage to the first network adapter. A second processor circuitry is for transferring data using a second path through the second output to the second buffer storage through the error correction module and from the second buffer storage to the second network adapter, wherein the second processor circuitry is responsive to an error in the storage module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.