Serial bus system for shadowing registers
US5748911A · kind A · utility
29Cited by
6References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Jul 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low latency serial bus system for shadowing registers between first and second digital devices. Either the first device or the second device may initiate a data transfer cycle on the serial bus when data in a shadowed register of that device has changed. The data transfer cycle includes a first frame where data is transferred from the first device to the second device and a second frame where data is transferred from the second device to the first device. The devices do not initiate a subsequent data transfer cycle for changed data if the changed data can be transferred in the current data transfer cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.