Method and apparatus for using a direct memory access unit and a data cache unit in a microprocessor
US5749092A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1997 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Jan 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0837
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor and method which allows data consistency to be maintained between a memory which is external to the microprocessor and a data cache unit. The microprocessor has a central processing unit coupled to a local bus. A direct memory access unit coupled to the central processing unit for loading data from and storing data to the direct access memory unit. The local bus is coupled to a system bus and has a bus control unit controlling the loading and storing of data on the system bus. The system bus transfers data external to the microprocessor using the bus control unit upon instructions from the central processing unit. A data cache unit is coupled to the local bus and selectively stores a copy of data loaded by the bus control unit and receives a memory address from the local bus during a memory access by either the central processing unit or the direct memory access unit. The microprocessor employs a mechanism that invalidates copy data when the memory access is a store by the direct memory access unit when a cache hit is detected. Further, the microprocessor employs a mechanism that designates as non-cacheable the loading of data by the direct access memory unit, even…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.