High speed customizable logic array device
US5751165A · kind A · utility
17Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1995 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Aug 18, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A very high speed customizable logic array device comprising: PA1 a substrate having at least one gate layer and at least first, second and third metal layers formed thereon, the gate layer including a multiplicity of identical unit logic cells, PA1 the customizable logic array device including at least three of the following functionalities: PA1 NAND, NOR, inverter, AND and OR and further being characterized in that the ratio between the rise time and the fall time of the logic cells embodying each of the at least three functionalities is constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.