Fail-fast, fail-functional, fault-tolerant multiprocessor system

US5751932A · kind A · utility

Assignee

• Tandem Computers Incorporated · US

Inventors

• Robert W. Horst · San Jose, US
• William E. Baker · Austin, US
• Randall G. Banton · Austin, US
• John M. Brown · Leander, US
• William F. Bruckert · Marlborough, US
• William P. Bunton · Pflugerville, US
• Gary F. Campbell · Palo Alto, US
• John Coddington · Austin, US
• Richard W. Cutts, Jr. · Georgetown, US
• Barry L. Drexler · Oakdale, US
• Harry Frank Elrod · Austin, US
• Daniel L. Fowler · Kentwood, US
• David J. Garcia · Los Gatos, US
• Paul N. Hintikka · Austin, US
• Geoffrey Ignatius Iswandhi · Sunnyvale, US
• Douglas E. Jewett · Austin, US
• Curtis Willard Jones, Jr. · Austin, US
• James S. Klecka · Rockdale, US
• John C. Krause · Georgetown, US
• Stephen G. Low · Austin, US
• Susan S. Meredith · Hillsboro, US
• Steven C. Meyers · Round Rock, US
• David P. Sonnier · Austin, US
• William J. Watson · Austin, US
• Patricia L. Whiteside · Austin, US
• Frank A. Williams · Austin, US
• Linda Ellen Zalzala · Austin, US

Key dates

• Filing date: Jun 7, 1995
• Grant date: May 12, 1998
• Expiry date: Jun 7, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L12/56
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, with…