Non-blocking fault-tolerant gamma network for multi-processor system
US5751934A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1996 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Nov 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17393
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A non-blocking fault tolerant gamma network for a multi-processor system is disclosed, including: N dual links respectively connected to n source nodes, and for transmitting data input; a first stage made up with n 2.times.3 switching devices for outputting data transmitted from the N dual links; a second stage made up with n 3.times.4 switching devices for outputting data output from the first stage; a third stage to n-1 stage made up with (n-2).times.N 4.times.4 switching devices for receiving data output from the second stage at the third stage and outputting the data to n-1 stage; an n stage made up with n 4.times.2 circuits for receiving data output from the n-1 stage and outputting the data; and n dual links connected to n destination nodes for transmitting data output from the n stage, whereby the links, which connect the n source nodes, switching devices of the interconnection network and n destination nodes, are designed according to the connection formula of the certain regulation, thus simultaneously set all paths between a plurality of sources and a plurality of destinations, and tolerate a single-switching fault or a single-link fault in the interconnection network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.