System and method for enhancing computer operation by prefetching data elements on a common bus without delaying bus access by multiple bus masters
US5751994A · kind A · utility
11Cited by
8References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 10, 1997 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Feb 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for managing data elements in a memory system. The memory system is accessible by a plurality of bus masters connected by a bus to the system. Code data elements to be read are predicted. The predicted code data elements are then transferred within the memory system from a slow to high speed memory without delaying memory access requests for data from the bus masters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.