System for minimizing latency data reception and handling data packet error if detected while transferring data packet from adapter memory to host memory
US5752078A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1995 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Jul 10, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system within a data processing system are disclosed for receiving information from a communications network. The data processing system includes a communications adapter, having an adapter memory, and a host memory. The communications adapter is coupled to the communications network, which transmits information to the data processing system in packets including a packet header and packet data. According to the present invention, a portion of a packet of information is received from the communications network at the adapter memory within the communications adapter. The portion of the packet of information includes at least a packet header that specifies a length of the packet of information and a destination address within the host memory. In response to receipt of the portion of the packet of information, a transfer of the packet of information from the adapter memory to the host memory is prepared prior to receipt of a final portion of the packet of information at the adapter memory. The packet of information is then transferred from the adapter memory to addresses within the host memory beginning with the destination address. Since the transfer is prepared before pa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.