Dynamic non-coherent cache memory resizing mechanism
US5752255A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 3, 1997 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Feb 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic cache resizing mechanism permitting a non-coherent cache memory to be altered in size during the operation thereof. A cache utilization monitoring system determines whether the cache size is optimised for a particular application and environment, and if it is not, modifies a selection process to resize the cache address space. The non-coherent property of the cache is utilized to permit the change of selection process during use, and the choice of selection process may be effected to take into account the proportion of live cache entries which will remain accessible after resizing, and the proportional change in size of the cache during a resizing operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.