Non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture and programming/erasing/reading method for the same
US5753950A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 10, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Apr 10, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An object of the present invention is to contribute to increase of storage capacity of a memory and to cope with an nonlinear parasitic resistance. The non-volatile memory have a cell applying to multi-bit data by means of a double layered floating gate architecture. The cell comprises: heavily doped layers (drains 3.sub.0 -3.sub.2 and source 2) being formed separated from each other along an arrangement direction L in a semiconductor substrate; a first floating gate 4A being disposed along a direction orthogonal to the direction L between the drains and source above the semiconductor substrate; second floating gates 4B.sub.1, 4B.sub.2 which respectively extend across the first floating gate above the first floating gate and lie along the direction L, close to the drain; program gates 6.sub.1, 6.sub.2 disposed correspondingly to one of the second floating gates; and a control gate 5 extending across the gate 4A above the gate 4A and being disposed along the direction L, close to the source. Since the second floating gates individually store carriers corresponding to a data bit and the first floating gate determines a threshold voltage in accordance with a sum amount of carriers sto…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.