Adaptive power management processes, circuits and systems
US5754436A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Nov 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system (100) for computer power management for a computer (102) having a clock (706), includes a plurality of sampling circuits (2360, 2350, 4630, 4720, 4810, 3400, 5300, 5400) responsive to different system activity levels and producing system activity signals representative of the system activity levels. More circuitry (120, 106, 4640) is responsive to the system activity signals and supplies weighted activity output signals adjustably weighting the system activity levels. Filter circuitry (702, 4680) continually responds to the weighted activity output signals to produce a series of duty cycle-related control signals (TONTOFF) representative of directions to pulse-width modulate (MASKCLK) the clock of the computer with such duty cycle. Other devices, systems and methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.