Method and apparatus for setting a bit-serial filter to an all-zero state
US5754455A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Apr 10, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0201
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Bit-serial digital filters use numerous flip-flops, which must be reset to a known, all-zero state for testing and start-up purposes. A method for setting a bit-serial digital filter to an all-zero state uses non-resettable flip-flops, which eliminates the increased gate count and current drain overhead of resettable flip-flops. A bit-serial digital filter is constructed using non-resettable flip-flops such as simple non-resettable D flip-flops. When a reset signal is initiated, a reset controller (350) sends an all-zero signal to reset gates (301, 321) positioned at the input to the digital filter and in each feedback loop or unit-delay path. Meanwhile, a bit-serial controller (250) cycles through its control signals to emulate the operation of the bit-serial filter. In two word cycles, each flip-flop in the digital filter will be set to a known, all-zero state, and the all-zero signal is removed to allow normal operation of the filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.