Byte-parallel system for implementing reed-solomon error-correcting codes
US5754563A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 11, 1995 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Sep 11, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed byte-parallel pipelined error-correcting system for Reed-Solomon codes includes a parallelized and pipelined encoder and decoder and a feedback failure location system. Encoding is accomplished in a parallel fashion by multiplying message words by a generator matrix. Decoding is accomplished with or without byte failure location information by multiplying the received word by an error detection matrix, solving the key equation and generating the most-likely error word and code word in a parallel and pipelined fashion. Parallelizing and pipelining allows inputs to be received at very high (fiber optic) rates and outputs to be delivered at correspondingly high rates with minimum delay. The error-correcting system can be used with any type of parallel data storage or transmission media to create an arbitrary level of fault-tolerance and allows previously considered unreliable media to be effectively used in highly reliable memory or communications systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.