Parallel packetized intermodule arbitrated high speed control and data bus
US5754803A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Jun 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70702
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A parallel packetized intermodule arbitrated high speed control data bus system which allows high speed communications between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing operating at 12.5 MHz, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocols. Bus arbitration is performed over a dedicated serial arbitration line and each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.