Data storage apparatus and method with two stage reading
US5754816A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Jul 2, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data memory is described in which data words comprising access control bits and further bits are stored at each memory location 34. When a particular memory location is addressed, then the access control bits stored at that memory location are output to control logic 12, 46 that serves to generate a valid access signal. The valid access signal is fed back to the selected memory location and controls whether the further bits stored at that memory location are output. If access to those further bits is not permitted by the access control bits, then the further bits are not output and power is saved. The control logic is responsive to hardware and software flags in addition to the access control bits. The system is particularly suited for use in conjunction with a cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.