Architecture and method for sharing TLB entries through process IDS
US5754818A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Mar 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address translation control circuit which operates in connection with a processor and a translation look-aside buffer ("TLB") to perform virtual-to-physical address translations through shared entries of the TLB. The address translation control circuit comprises a primary context storage element, a group context storage element, a context matching circuit, a comparing unit and a logic unit. The context matching circuit is coupled to primary and group context storage elements to receive their context numbers and reads a context identification number and a context select bit value from a chosen translation entry of the TLB. Concurrently, the comparing unit compares the virtual address contained in that entry with the virtual address requested for translation by the processor. The logic unit receives the outputs from the context matching circuit and the comparing unit and signals operating system software whether an appropriate translation has been found in the TLB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.