Synchronous dynamic memory device capable of operating over wide range of operation frequencies
US5754838A · kind A · utility
86Cited by
4References
5Claims
0Family size
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Key dates
| Filing date | Dec 21, 1995 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Dec 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a synchronous DRAM, internal clock signals in synchronism with clock signals fed from an external unit are generated by a PLL circuit or a DLL circuit to eliminate signal delays. In order to provide a dynamic RAM that is capable of stably operating with clock signals over a wide range of frequencies; a change-over circuit is provided which changes the range of variable frequencies of the PLL circuit or changes the variable delay time of the DLL circuit based upon mode-setting information fed from an external unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.