Extended symmetrical multiprocessor architecture
US5754877A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1996 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Jul 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for an extended multiprocessor (XMP) computer system is provided. The XMP computer system includes multiple SMP nodes. Each SMP node includes an XMP interface and a repeater structure coupled to the XMP interface. The SMP nodes are connected to each other by unidirectional point-to-point links. The repeater structure in each SMP node includes an upper level bus, one or more transaction repeaters coupled to the upper level bus. Each transaction repeater broadcasts transactions to bus devices attached to a lower level bus, wherein each transaction repeater is coupled to a separate lower level bus. Transaction repeater includes a queue and a bypass path. Transaction originating in a particular SMP node are stored in the queue, whereas transactions originating in other SMP nodes bypass the incoming queue to the bus device. Multiple transactions may be simultaneously broadcast across the point-to-point link connections between the SMP nodes. However, transactions are broadcast to the SMP nodes in a defined, uniform order. A control signal is asserted by the XMP interface so that a transaction is received by bus devices in the originating node from the incoming queues at …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.