Electrically erasable and programmable read only memory cell with split floating gate for preventing cell from over-erase
US5757044A · kind A · utility
23Cited by
4References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 26, 1995 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Oct 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5612
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating gate type field effect transistor has a plurality of floating gate sub-electrodes on a lower gate oxide layer electrically isolated from one another; even if one of the floating gate sub-electrodes changes a part of a channel region thereunder to depletion state due to an over-erase, the over-erase does not affect the function of the floating gate type field effect transistor, because another sub-electrode transfers and cuts off channel current depending upon the amount of electrons accumulated therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.