Digitally controlled programmable attenuator
US5757220A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1996 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Dec 23, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/0088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digitally controlled programmable attenuator maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers that are connected between the respective taps and a common output, and a fixed gain stage that sets the attenuator's overall gain/attenuation. The buffers maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0.2.degree. at frequencies up to 300 MHz for 30 dB of gain variation has been realized. The buffers can be implemented with complementary bipolar or BiCMOS processes
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.