Bias circuit for a power amplifier
US5757229A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1996 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Jun 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/432
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for amplifying an RF input signal using a power amplifier (105, 107 or 205, 207) comprises the steps of dividing or quadrature splitting (103) the RF input signal into an in-phase signal and a quadrature phase signal. A carrier amplifier bias input (111, 211) signal is varied relative to the magnitude of the RF input signal. A peaking amplifier bias input (113, 213) signal is varied relative to the magnitude of the RF input signal. The in-phase signal is amplified using a carrier amplifier (105, 205) to produce a first amplified signal. The quadrature phase signal is amplified using a peaking amplifier (107, 207) to produce a second amplified signal. The first amplified signal and the second amplified signal are combined (115, 117), in phase, to produce an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.