Method for dynamically biasing an amplifier and circuit therefor
US5757237A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1996 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Aug 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/222
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplifier (50) includes two transistors (11, 21) and a dynamic biasing circuit (52). The dynamic biasing circuit (52) uses a sampling circuit (54) to generate a bias adjusting signal proportional to the amplitude of an AC signal at a drain electrode of the first transistor (11). The bias adjusting signal is combined with a constant voltage bias signal to generate a dynamic biasing signal applied to a gate electrode of the second transistor (21). As the gain of the first transistor (11) decreases, the amplitude of the AC signal at its drain electrode decreases. Thus, the dynamic biasing circuit (52) generates a lower dynamic biasing signal at the gate electrode of the second transistor (21), thereby decreasing a quiescent drain current in the second transistor (21) and improving the efficiency of the amplifier (50) at low output power levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.