Expediting blending and interpolation via multiplication
US5757377A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1996 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | May 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry combines a first operand A.sub.0, a second operand A.sub.1, and a third operand X in a blend function to produce a result Z. The result Z has a value equal to X*A.sub.0 +(1-X)* A.sub.1. The circuitry includes a plurality of logic gates organized in rows. When performing the blend operation each logic gates selects either a bit of the first operand A.sub.0 or a bit of the second operand A.sub.1. The selection for each logic gate depends upon bits of the third operand X. More specifically, each of the plurality of rows of logic gates selects the first operand A.sub.0 as output when an associated bit of the third operand X is at logic 1, and selects the second operand A.sub.1 as output when the associated bit of the third operand X is at logic 0. In addition to output generated by the plurality of rows of logic gates, a correction term is generated. For the blend operation, the correction term generated is the second operand A.sub.1. Partial product circuitry sums outputs of each row of logic gates and the correction term, to produce the result Z, so that the result Z has a value equal to X*A.sub.0 +(1-X)*A.sub.1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.