Electrical signal jitter and wander measurement system and method
US5757652A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1995 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Dec 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0062
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electrical signal jitter and wander measurement system (30) operates in real time and digitally controls bandwidths over which the measurements are performed. A digital phase-lock loop ("PLL") (34) includes a phase detector (44), low pass filters (48, 56), an analog-to-digital converter ("ADC") (54), a digital signal processor ("DSP") (32), a direct digital synthesizer ("DDS") (38), and a tracking oscillator (39). The phase detector receives an input signal that is compared with a signal derived from the DDS. The phase detector signal contains wander and jitter data that are filtered and digitized by the ADC. The DSP receives the data and performs a proportional integral control function to lock the PLL by digitally controlling the DDS frequency. The DDS generates a clock signal at a precise rate determined by the phase accumulation registers. The tracking oscillator locks to multiples of the DDS frequency to increase the resolution of the phase measurement. A master reference clock (40) controls the PLL with a stability and accuracy sufficient to measure low frequency wander. Wander data are available from the DSP as an integral of the DDS operating frequency. The DSP also perf…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.