Balanced resistance load type SRAM cell
US5757694A · kind A · utility
7Cited by
4References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 28, 1996 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Mar 28, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a static semiconductor memory device including first and second power supply lines for a first voltage, a third power supply line for a second voltage, first and second nodes, and first and second drive transistors connected between the first and second nodes and the third power supply line, a first load resistor is connected between the first power supply line and the first node, and a second load resistor is connected between the second power supply line and the second node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.