Word-wise processing for reed-solomon codes
US5757826A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 1995 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Jul 12, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A word-wise encoder circuit that processes word formatted data blocks in response to a word clock signal and generates redundancy in accordance with an 8 bit symbol code. The encoder is provided with two parallel data paths, each receiving one of the respective bytes halves of the received data words during one word clock period to implement an 8 bit symbol code in response to a word clock signal. The word-wise encoder replicates, in one word clock period, the state of the registers in a standard sequential encoder after two consecutive bytes have been processed in response to a byte clock. In a preferred embodiment, a word-wise encoder is used to implement a Reed-Solomon data integrity code. In this example, the word-wise encoder generates redundancy that is appended to associated data blocks temporarily stored in a block buffer memory within a data channel to provide a mechanism for detecting data errors caused by the buffer. A reduced hardware implementation of a word-wise encoder circuit is disclosed wherein a special choice of generator polynomial and Galois field representation allows a Galois field multiplier to be eliminated. In this embodiment, the encoder generates two by…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.