Clock recovery circuit
US5757872A · kind A · utility
18Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1994 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Nov 30, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0626
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit is coupled to an elastic storage circuit such as a FIFO circuit. More specifically, a first input of the elastic storage circuit is electrically connected to an output of the clock recovery circuit. A second input for accepts a data signal representing an input data stream from a communications medium. A third input accepts a local clock signal. The resultant circuit may be used in receiver's for communications systems to help alleviate the problems of frequency mismatch and jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.