Fault handling and recovery for system having plural processors
US5758053A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Feb 1, 1994 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Feb 1, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parallel processors communicate with each other over a network by transmitting messages that include destination processor information. A message controller for each processor in the network receives the messages and checks for faults in the message, particularly in the destination processor number contained in a first word of the message. If a fault occurs in the destination processor number, then the faulty message is transmitted to an appropriate processor for handling the fault. In this way the network operation is not suspended because of the fault and the message is not left in the network as a result of the error occurring in the destination processor number. The processor to which the faulty message is directed is determined by a substitute destination processor number contained in the message or is predetermined and set in another way, such as by a service processor. To recover from the fault, the processor receiving the faulty message can request that the message be retransmitted or the error can be corrected using an ECC, for example. If the faulty message cannot be retransmitted, then the processor or the host processor can request that the job to which the faulty messa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.