Verification support system
US5758123A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1995 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Apr 11, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A verification support system wherein before a CPU mounted circuit is actually made such circuit model and an ICE model are made virtually and verification of such circuit model is performed using logic simulation on the ICE model; and when an error is found execution and verification up to the error point are omitted and are performed immediately after the error point to correct the error. A waveform, obtained by logic simulation, and a partially enlarged waveform thereof are displayed on different display regions for each time period and a display region is provided for saving a displayed waveform obtained when logic simulation is stopped. In another aspect of the invention, before an actual system is made by PLC, such PLC model is verified, and a test program is carried out to obtain verification when a process model is detached from the PLC model, and a sequence program is carried out by using a general purpose simulator with a debugging function. The verification system enhances efficiency of development of a CPU mounted circuit, and development of a sequence control system using a PLC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.