Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register
US5758141A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1995 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Feb 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45554
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.