Interrupt vectoring for optionally architected facilities in computer systems
US5758168A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1996 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Apr 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application-level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler. Only the code which is used to save state and check to see if an exception is registered is in the kernel, and this part of the exception handling code is implementation-independent. i.e., the same for all implementations of this processor architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.