System for preventing corruption during CPU reset
US5758170A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1995 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Mar 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a system and method for preventing a computer from initiating new cycles after a user has requested a reboot of the computer. The invention includes a programmable logic device that monitors the reset request (SRESET) signal, and in response places the central processing unit (CPU) of the computer in a hold state. The programmable logic device does this by issuing a hold (HOLD) signal to the CPU and receives back from the CPU a hold acknowledge (HLDA) signal. After the HLDA signal is received, the programmable logic device issues a CPU reset (RESETCPU) signal, which causes the CPU to reset after a certain number of clock cycles have passed. By placing the CPU in a hold state, the programmable logic device prevents the CPU from initiating new cycles just prior to resetting, which could result in corruption of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.