Resistless methods of fabricating FETs
US5759880A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1997 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jan 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0335
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating semiconductor devices including forming a plurality of layers of semiconductor material on the surface of a substrate, forming a mask without using a resist on the layers which can be disassociated in-situ, removing an unmasked portion of the layers to form a semiconductor device with a gate region and opposed exposed source and drain surfaces, selectively growing source and drain contact regions on the exposed source and drain surfaces respectively, the contact regions defining opposed sidewalls adjacent the gate region, disassociating the mask, forming sidewall spacers on the sidewalls, forming a metal contact on the source, drain and gate regions with the spacers preventing intercontact therebetween, and depositing a passivating layer over the semiconductor device, with all of the previous steps being performed in-situ in a modular equipment cluster.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.