Variable width low profile gate array input/output architecture
US5760428A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jan 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate array masterslice having a minimal input/output slot and variable pad pitch architecture is disclosed. In the masterslice, many identical input/output slots ring the periphery of a semiconductor substrate and contain only the special devices necessary for input/output circuits. Each of the input/output slots include (i) a first region containing a plurality of tuning transistors of different sizes, (ii) a second region having one or more PMOS transistors, each of a size greater than any one of the plurality of tuning transistors, (iii) a third region having one or more NMOS transistors, each of a size greater than any one of the plurality of tuning transistors, and (iv) a fourth region containing one or more devices for providing electrostatic discharge protection. One to four PMOS transistors are provided in the second slot region and one to four NMOS transistors are provided in the third slot region. A plurality of bonding pads are provided, at least some of which are electrically connected to at least some of the input/output slots such that the plurality of bonding pads may have a variable bonding pad pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.