Method and apparatus for testing semiconductor integrated circuits
US5760599A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Aug 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31924
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A current detecting resistance is inserted somewhere in a path for feeding a power source current to a supply voltage terminal VDD of a DUT from a power source of a testing apparatus, and from the potential difference at both ends, a pulse form change due to the state transition of a CMOS circuit in the DUT contained in the power source current is detected. The number of pulse form changes is counted by a counter. In the DUT, a test pattern is applied from a driver, an expected value preset according to the test pattern and the count of the counter are compared, and it is judged whether or not the DUT is in good quality. The current due to a pulse form transition to be detected by the current detecting resistance is larger than the current flowing when the CMOS circuit in the DUT is in a static state, and therefore, the resistance value of the current detecting resistance may be set smaller, so that the time required for testing may be shortened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.