Method and circuit arrangement for the generation of a channel-coded binary signal
US5760717A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jul 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4906
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Low-redundancy codes are increasingly being striven for, such codes thus inevitably requiring comparatively long code words. However, since the memory requirement for coding tables increases considerably with the length of the code words, the use of code tables is then no longer expedient. Instead, coding is then effected by selecting the optimum code word in each case from a plurality of different code words taking account of coding; prescriptions and spectral decisions. For this purpose, the maximum run length for each code word is also determined, inter alia, but the spectral decisions are decisive as long as the maximum run length does not exceed a predetermined maximum value. Provided that the end of one code word and the beginning of a succeeding code word have the same binary value, incorrect decisions in the selection of the optimum code word may arise in the region where the synchronizing pattern is keyed in. According to the invention, therefore, the bit pattern (16) serving for synchronization is changed (17) prior to the determination of the code word which is optimum for generating the signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.