Error variance circuit
US5760756A · kind A · utility
7Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1995 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Nov 16, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0247
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An error variance circuit, wherein a reproduced error, as detected at an error detection circuit, is added to the image signal of the input signal picture element of n bits, and wherein a variance output signal is converted into a signal of m (.ltoreq.n-l) bits and outputted to a display panel, includes a clear circuit that clears error at each frame and forcibly reduces the prior error to zero thus preventing excessive noise from preceding frames and non-image duration causing flickering of picture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.