Driving pulse output limiting circuit
US5761055A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 1, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Aug 1, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/538
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In a driving pulse output limiting circuit, ideal switching operations are performed in all oscillation permitting frequencies and in all impedance conditions free from excessive surge current stresses due to excessive driving pulse width. While a charging current or a discharging current is being supplied to a capacity 11 which is connected between both ends of a switching element 3 or between windings of a main transformer 7, voltages are generated between both ends of a switching element 2 and between both ends of the switching element 3. A pulse voltage which is generated accordingly between both ends of an impedance element 13 connected in series to the capacity 11 is detected with a charging current detecting circuit 32 or a discharging current detecting circuit 35, and outputs of these circuits are applied to pulse limiting circuits 30 and 31 for blocking driving input signals to the driving circuit of switching elements 2 and 3, thereby limiting driving pulses to the switching elements so that these elements are driven after the pulse voltages applied between both ends thereof are lowered to about 0V!.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.