Left and right justification of single precision mantissa in a double precision rounding unit
US5761103A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1995 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Mar 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double precision rounding unit is employed for both single and double precision rounding. Rounding double precision mantissas employs the double precision rounding unit normally. For rounding single precision mantissas, the single precision mantissa is both left and right justified at the inputs of the double precision rounding unit. The N bits of the single precision number are supplied to a set of N least significant bit inputs of the double precision rounding unit. The N bits of the single precision number are also supplied to a set N of most significant bit inputs of the double precision rounding unit. The central M bits, which are between the set of N least significant bit inputs and the set of N most significant bit inputs are supplied with zeros. The double precision rounding unit is operated normally with the single precision input. A single precision/double precision masking unit at the output of the double precision rounding unit selects the proper bits. In double precision mode, all the output bits of the double precision rounding unit are valid. In single precision mode, only the N most significant outputs of the double precision unit are valid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.