Soft error suppressing resistance load type SRAM cell
US5761113A · kind A · utility
3Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1995 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Oct 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an SRAM cell including two cross-coupled inverters each having a first resistance element and a drive MOS transistor, a second resistance element is connected between the first and the drive MOS transistor. A gate electrode of the drive MOS transistor of one of the inverters is connected between the first and second resistance elements of the other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.