Sense amplifier circuit of a nonvolatile semiconductor memory device
US5761123A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jun 13, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit for a nonvolatile semiconductor memory device, with NAND structured cells, includes a bit line isolation section located between a pair of bit lines connected to a memory cell array and a pair of sub-bit lines connected to an input/output gate circuit, a latch type voltage-controlled current source having n-channel MOS transistors connected to the sub-bit lines, and a switching section connected between the voltage-controlled current source and a signal line. The bit lines are electrically isolated from the sub-bit lines by provision of a bit line isolation section receiving an isolation control signal during the sensing operation. The sense amplifier circuit sensing operation is not affected by bit line load impedance and, accordingly, the sensing speed is improved and peak current is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.