Method and apparatus for I/O multiplexing of RAM bus
US5761129A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1997 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Mar 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RAM and I/O controller is provided with logic for controlling access to a DRAM and to one or more input and/or output latches, each of which are coupled to a RAM data bus. The logic receives input signals such as a refresh request signal and a RAM access request signal from other circuits or devices, and outputs one or more associated control signals onto a RAM control bus, such as a RAS output signal or a CAS output signal. The logic includes at least one idle state during which the DRAM is in a RAS or CAS precharge period. During the idle state, the logic de-asserts the RAS or CAS output and asserts one or more control signals to the input and/or output latches so as to perform at least one write and/or read operation of miscellaneous data signals with the latches 112 and 114 of FIG. 2a over the temporarily idle RAM data bus. A method is also provided for I/O multiplexing a RAM bus by providing one or more control signals, such as a RAS signal and a CAS signal for a DRAM on a RAM control bus, and performing at least one read operation and/or write operation on a RAM data bus from circuits or devices, other than the DRAM, during one or more of the RAM's precharge cycles or perio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.