Edge-synchronized clock recovery unit
US5761255A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1995 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Nov 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock recovery unit for recovering a clock embedded in a data communication is disclosed. The clock recovery unit includes an oscillator (50) operating at a frequency close to that of the clock embedded in the data communication. The clock recovery unit also includes an edge detector (30) that produces a synchronization pulse with each transition in the data communication. The edge detector is coupled to the oscillator to force a transition in the oscillator in synchronization with the synchronization pulse produced by the edge detector. A start-up latch (10) that starts and stops the oscillator also forms part of the clock recovery unit. The start-up latch starts the oscillator at the beginning of the data communication, with no preamble bits required. For low-power consumption in stand-by mode, a counter (40) coupled to the start-up latch stops the oscillator after data has been determined not to be present for a preset period of time. Preferably, the start-up latch, edge detector, counter, and oscillator are incorporated into an Application Specific Integrated Circuit (ASIC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.