Parallel architecture for generating pseudo-random sequences
US5761265A · kind A · utility
1Cited by
8References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 24, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Apr 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/583
- WIPO fieldEngines, pumps, turbines
- WIPO sectorMechanical engineering
Abstract
A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.