Dynamic bus reconfiguration logic
US5761455A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 1995 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Feb 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17337
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel processing system is provided with a plurality of processors and a plurality of memories, and bus units with arbitration coupling the processors and memories. A bus unit provides a pathway between one processor and the bus unit's respective memory. Each bus unit arbitrates multiple simultaneous access requests for its respective memory and communicates its decisions to other bus units so that a memory access requiring multiple memories will only occur if all those memories are available. The coupling of processors to memories can change, dynamically, each bus cycle without the need for setup before the bus cycle either by pipelining or having unused bus cycles. In a specific embodiment, the memory access information is provided on high order address lines, where the processor logically accesses different memory address spaces to make different accesses, thereby sharing memory with other processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.