Method and system for increased instruction synchronization efficiency in a superscalar processsor system utilizing partial data dependency interlocking
US5761473A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1993 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jan 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for increased instruction synchronization efficiency in a superscalar processor system which includes instructions having multiple source and destination operands. Simultaneous dispatching of multiple instructions creates a source-to-destination data dependency problem in that the results of one instruction may be necessary to accomplish execution of a second instruction. Data dependency hazards may be eliminated by prohibiting each instruction from dispatching until all possible data dependencies have been eliminated by the completion of preceding instructions; however, instruction dispatch efficiency is substantially decreased utilizing this technique. Data dependency interlock circuitry may be utilized to clear possible data dependency hazards; however, the complexity of such circuitry increases dramatically as the number of interlocked sources and destinations increases. The method and system of the present invention utilizes data dependency interlock circuitry capable of interlocking two source operands by two destination operands for each instruction. Instructions having three or more source operands are interlocked at the dispatch stage for the first two …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.