Operand dependency tracking system and method for a processor that executes instructions out of order
US5761474A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | May 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operand dependency tracking system monitors operand dependencies, among instructions in a processor that executes instruction out of order. The processor has queues that are configured to execute the instructions out of order. An arithmetic queue (aqueue) executes arithmetic instructions and a memory queue (mqueue) executes memory instructions. The aqueue has aslots for receiving respective instructions. Each aslot includes a set dependency latch, a use dependency latch, valid operand (valop) propagation logic, and valid dependent (valdep) logic. The set dependency latch produces a set dependency signal that indicates whether a local instruction in a local slot is to produce operand data that is to be used by a remote dependent instruction that follows the local instruction in program order. The use dependency latch produces a use dependency signal that indicates whether the local instruction is to use operand data that is to be produced by a remote producer instruction that precedes the local instruction in the program order. The valop propagation logic in each local aslot produces a valop signal(s) that is forwarded to the immediately following adjacent aslot to indicate respe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.